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International Journal on Smart Sensing and Intelligent Systems

Professor Subhas Chandra Mukhopadhyay

Exeley Inc. (New York)

Subject: Computational Science & Engineering, Engineering, Electrical & Electronic


eISSN: 1178-5608



VOLUME 10 , ISSUE 2 (June 2017) > List of articles


S. D. Thabah * / M. Sonowal * / P. Saha *

Keywords : Multi-operand adders,  synthesis results,  tree adders,  Verilog.

Citation Information : International Journal on Smart Sensing and Intelligent Systems. Volume 10, Issue 2, Pages 327-340, DOI: https://doi.org/10.21307/ijssis-2017-214

License : (CC BY-NC-ND 4.0)

Received Date : 15-February-2017 / Accepted: 15-April-2017 / Published Online: 01-June-2017



In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality of the adders have been verified using Verilog hardware description language and synthesized in Xilinx ISE. The device chosen for implementation is Virtex 6 (XC6VLX240T) with FF1156 package. Simulation results show that Wallace tree adder is the fastest adder and consumes least amount of power. The Wallace tree adder
also consumes the least amount of hardware resources as per the synthesis results.

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