EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

Publications

Share / Export Citation / Email / Print / Text size:

International Journal on Smart Sensing and Intelligent Systems

Professor Subhas Chandra Mukhopadhyay

Exeley Inc. (New York)

Subject: Computational Science & Engineering, Engineering, Electrical & Electronic

GET ALERTS

eISSN: 1178-5608

DESCRIPTION

33
Reader(s)
89
Visit(s)
0
Comment(s)
0
Share(s)

VOLUME 10 , ISSUE 2 (June 2017) > List of articles

EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

S. D. Thabah * / M. Sonowal * / P. Saha *

Keywords : Multi-operand adders,  synthesis results,  tree adders,  Verilog.

Citation Information : International Journal on Smart Sensing and Intelligent Systems. Volume 10, Issue 2, Pages 327-340, DOI: https://doi.org/10.21307/ijssis-2017-214

License : (CC BY-NC-ND 4.0)

Received Date : 15-February-2017 / Accepted: 15-April-2017 / Published Online: 01-June-2017

ARTICLE

ABSTRACT

In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality of the adders have been verified using Verilog hardware description language and synthesized in Xilinx ISE. The device chosen for implementation is Virtex 6 (XC6VLX240T) with FF1156 package. Simulation results show that Wallace tree adder is the fastest adder and consumes least amount of power. The Wallace tree adder
also consumes the least amount of hardware resources as per the synthesis results.

Content not available PDF Share

FIGURES & TABLES

REFERENCES

  1. R. D. Kenney and M. J. Schulte, “High-Speed Multioperand Decimal Adders”, IEEE Transactions on Computers, vol. 54, no. 8, pp. 953-963, Aug. 2005.
  2. N. Chabini and S. Belkouch, “Area and delay aware approaches for realizing multioperand addition on FPGAs using two-operand adders”, in Proc. of IEEE/ACS International Conference of Computer Systems and Applications (AICCSA), pp. 1-4,2015.
  3. P. Kumar and R. K. Sharma, “Real-time fault tolerant full adder design for critical applications”, Engineering Science and Technology, an International Journal, vol. 19 no.9, pp. 1465–1472, Sept. 2016.
  4. M. Sushmidha and B. Premalatha “Design of high performance parallel self timed adder”, in Proc. of Int. Conf. on Communication and Signal Processing (ICCSP) pp.1400 – 1404, 2016
  5. P. I. Balzola, M. J. Schulte, J. R. J. Glossner and E. Hokenek “Design Alternatives for Parallel Saturating Multioperand Adders”, in Proc. of IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors, pp. 172-177, 2001.
  6. L. Dadda, and V. Piuri, Pipelined Adders, IEEE Transactions on Computers, vol. 45,no. 3, pp. 348-356, March 1996.
  7. J. Saini, S. Agarwal and A. Kansal, “Performance, Analysis and Comparison of Digital Adders”, in Proc. Int. Conf. on Advances in Computer Engineering and Applications(ICACEA), pp. 80-83, 2015.
  8. S. Singh and D. Waxman, “Multiple Operand Addition and Multiplication”, IEEE Transactions on Computers, vol. C-22, no. 2, pp. 113-120, Feb. 1973.
  9. A. Albeck and S. Wimer, “Energy efficient computing by multi-mode addition”,Integration the VLSI journal, vol. 55, no. 9, pp. 176-182, Sept. 2016.
  10. J. Hormigo, J. Villalba and E. L. Zapata, “Multioperand Redundant Adders on FPGAs”,IEEE Transactions on Computers, vol. 62, no. 10, pp. 2013-2025, Oct. 2013.
  11. U. Cini and O. Kurt “MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding”, Int. Conf. on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 1-4, 2016
  12. J. Villalba, J. Hormigo, J. M. Prades and E. L. Zapata, “On–line Multioperand Addition Based on On–line Full Adders∗”, in Proc. Int. Conf. on Application-Specific Systems,Architecture Processors (ASAP'05), pp. 322-327, 2005
  13. H. Parandeh-Afshar, P. Brisk and P. Ienne “Efficient Synthesis of Compressor Trees on FPGAs”, in Proc. of Asia and South Pacific Design Automation Conference, Mar.2008, pp. 138-143
  14. Hardware Algorithm for Arithmetic Modules:http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html
  15. H. Al-Twaijry and M. Flynn “Performance/Area Tradeoff in Booth Multipliers”Technical Report, Nov. 1995, Stanford University.
  16. W. Li and L. Wanhammar, “A complex multiplier using overturned-stairs adder tree,”in Proc. of IEEE Int. Conf. on Electronics, Circuits and Systems, pp. 21-24, 1999..
  17. S. J Piestrak, “Design of Residue Generators and Multi-operand Modular Adders using carry save adder”, IEEE Transactions on Computers, vol.43, no.1, pp. 68-77, January1994.
  18. A. Ibrahim and F. Gebali, “Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders”, Microelectronics Journal, vol. 46, no. 9, pp. 783–794, Sept.2015.
  19. I. Koren, Computer Arithmetic Algorithms. Englewood Cliffs, N.J.:Prentice-Hall, 1993.

EXTRA FILES

COMMENTS