DESIGN OF LOW POWER CARRY SKIP ADDER USING DTCMOS

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International Journal on Smart Sensing and Intelligent Systems

Professor Subhas Chandra Mukhopadhyay

Exeley Inc. (New York)

Subject: Computational Science & Engineering, Engineering, Electrical & Electronic

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VOLUME 10 , ISSUE 5 (December 2017) > List of articles

Special Issue

DESIGN OF LOW POWER CARRY SKIP ADDER USING DTCMOS

T.R.Dinesh Kumar / K.Mohana Sundaram / M.Anto Bennet / Aruna .R / Meena .B / M. Mohanapriya

Keywords : Carry skip adder, low power consumption, high performance, speed and delay parameters

Citation Information : International Journal on Smart Sensing and Intelligent Systems. Volume 10, Issue 5, Pages 284-294, DOI: https://doi.org/10.21307/ijssis-2017-252

License : (CC BY-NC-ND 4.0)

Received Date : 27-May-2017 / Accepted: 15-June-2017 / Published Online: 01-September-2017

ARTICLE

ABSTRACT

In the domain of VLSI design, the adders are always meant to be the most fundamental requirements for processors of high performance and other multicore devices. It is found that power dissipation is a major problem in the electronic devices. Power management integrated circuit (PMIC) is emphasized as battery-powered portable electronics such as smart phone are commonly used. In this paper we are designing a carry skip adder which consumes less power than the other conventional adders using dynamic threshold complementary metal oxide semiconductor (DTCMOS).Tthe circuit is designed using tanner EDA simulator of 32nm technology. Also the circuit is compared with the CMOS technology methods.

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