A Fault Detection Method for Combinational Circuits


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International Journal of Advanced Network, Monitoring and Controls

Xi'an Technological University

Subject: Computer Science, Software Engineering


eISSN: 2470-8038





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VOLUME 1 , ISSUE 1 (June 2016) > List of articles

A Fault Detection Method for Combinational Circuits

Ali Abbass Zoraghchian / Moslem Didehban / Mohammad Reza Mehrabian

Keywords : Soft Error, Transient Fault, Fault-Tolerance, Combinational Circuits, Full Adder

Citation Information : International Journal of Advanced Network, Monitoring and Controls. Volume 1, Issue 1, Pages 0-0, DOI: https://doi.org/10.21307/ijanmc-2016-004

License : (CC BY-NC-ND 4.0)

Published Online: 01-April-2018



As transistors become increasingly smaller and faster and noise margins become tighter, circuits and chip specially microprocessors tend to become more vulnerable to permanent and transient hardware faults. Most microprocessor designers focus on protecting memory elements among other parts of microprocessors against hardware faults through adding redundant error-correcting bits such as parity bits. How ever, the rate of soft errors in combinational parts of microprocessors is consider edas important as in sequential parts such as memory elements nowadays. The reason is that advances in scaling technology have led to reduced electrical masking .This paper proposes and evaluates a logic level fault-tolerant method based on parity for designing combinational circuits. Experimental results on a full adder circuit show that the proposed method makes the circuit fault- tolerant with less overhead in comparison with traditional methods. It will also be demonstrated that our proposed method enables the traditional TMR method to detect multiple faults in addition to single fault masking.

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